View LC72136_27836.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Ordering number : EN5038
CMOS LSI
LC72136, 72136M
PLL Frequency Synthesizer for Electronic Tuning
Overview
The LC72136 and LC72136M are PLL frequency synthesizers for use in radio/cassette players. They allow high-performance AM/FM tuners to be implemented easily.
Package Dimensions
unit: mm 3059-DIP22S
[LC72136]
Features
* High-speed programmable frequency divider -- FMIN: 10 to 160 MHz.....Pulse swallower (divide-by-two prescaler built in) -- AMIN: 2 to 40 MHz.........Pulse swallower 0.5 to 10 MHz......Direct division * IF counter IFIN: 0.4 to 12 MHz................For use as an AM/FM IF counter * Reference frequency -- Selectable from one of eight frequencies (crystal oscillator: 75 kHz) 1, 3, 5, 3.125, 6.25, 12.5, 15, and 25 kHz * Phase comparator -- Supports dead zone control -- Built-in unlock detection circuit -- Built-in deadlock clear circuit * Built-in MOS transistor for forming an active low-pass filter * I/O ports -- Dedicated output ports: 6 -- I/O ports: 2 -- Supports clock time base output * Serial Data I/O -- Supports CCB format communication with the system controller. * Operating ranges -- Supply voltage: 4.5 to 5.5 V -- Operating temperature: -20 to +70C * Packages --DIP22S/MFP24S
* CCB is a trademark of SANYO ELECTRIC CO., LTD. * CCB is SANYO's original bus format and all the bus addresses are controlled by SANYO.
SANYO: DIP22S
unit: mm 3112-MFP24S
[LC72136M]
SANYO: MFP24S
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
O3195HA (OT) No. 5038-1/23
LC72136, 72136M Pin Assignments
No. 5038-2/23
LC72136, 72136M Block Diagram
Specifications
Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Maximum supply voltage Symbol VDD max VIN1 max Maximum input voltage VIN2 max VIN3 max VO1 max Maximum output voltage VO2 max VO3 max IO1 max Maximum output current IO2 max IO3 max Allowable power dissipation Operating temperature Storage temperature Pd max Topr Tstg VDD CE, CL, DI, AIN XIN, FMIN, AMIN, IFIN IO1, IO2 DO XOUT, PD BO1 to BO5, BOF, IO1, IO2, AOUT BO1 AOUT, DO BO2 to BO5, BOF, IO1, IO2 Ta 70C: LC72136 (DIP22S) Ta 70C: LC72136M (MFP24S) Conditions Ratings -0.3 to +7.0 -0.3 to +7.0 -0.3 to VDD + 0.3 -0.3 to +15 -0.3 to +7.0 -0.3 to VDD + 0.3 -0.3 to +15 0 to 3.0 0 to 6.0 0 to 10.0 350 200 -20 to +70 -40 to +125 Unit V V V V V V V mA mA mA mW mW C C
No. 5038-3/23
LC72136, 72136M Allowable Operating Ranges at Ta = -20 to +70C, VSS = 0 V
Parameter Supply voltage Input high-level voltage Input low-level voltage Output voltage Symbol VDD VIH1 VIH2 VIL V O1 V O2 fIN1 fIN2 Input frequency fIN3 fIN4 fIN5 VIN1 VIN2-1 VIN2-2 Input amplitude VIN3 VIN4 VIN5-1 VIN5-2 VDD CE, CL, DI IO1, IO2 CE, CL, DI, IO1, IO2 DO BO1 to BO5, BOF, IO1, IO2, AOUT XIN: VIN1 FMIN: VIN2 AMIN: VIN3, SNS = 1 AMIN: VIN4, SNS = 0 IFIN: VIN5 XIN: fIN1 FMIN: f = 10 to 130 MHz FMIN: f = 130 to 160 MHz AMIN: fIN3, SNS = 1 AMIN: fIN4, SNS = 0 IFIN: fIN5, IFS = 1 IFIN: fIN6, IFS = 0 10 2 0.5 0.4 400 40 70 40 40 40 70 Conditions min 4.5 0.7 VDD 0.7 VDD 0 0 0 75 160 40 10 12 1500 1500 1500 1500 1500 1500 1500 typ max 5.5 6.5 13 0.3 VDD 6.5 13 Unit V V V V V V kHz MHz MHz MHz MHz mVrms mVrms mVrms mVrms mVrms mVrms mVrms
Guaranteed crystal Xtal XIN, XOUT* 75 kHz oscillator frequency Note: * Crystal oscillator recommended CI value CI 35 k (for a 75 kHz crystal) The circuit constants for the crystal oscillator circuit depend on the crystal used, the printed circuit board pattern, and other items. Therefore we recommend consulting with the manufacturer of the crystal for evaluation and reliability. The extremely high input impedance of the XIN pins means that applications must take the possibility of leakage into account.
Sample Oscillator Circuits 1. Seiko-Epson C-2-75kHz (CL = 11 pF)
2. Kyocera Corporation KF-38R5-09P0300 (CL = 9 pF)
No. 5038-4/23
LC72136, 72136M Electrical Characteristics at Ta = -20 to +70C, VSS = 0 V
Parameter Symbol Rf1 Internal feedback resistors Rf2 Rf3 Rf4 Internal pull-down resistors Internal output resistor Hysteresis Output high-level voltage Rpd1 Rpd2 Rd VHIS VOH1 VOL1 VOL2 VOL3 XIN FMIN AMIN IFIN FMIN AMIN XOUT CE, CL, DI, IO1, IO2 PD: IO = -1 mA PD: IO = 1 mA BO1: IO = 0.5 mA BO1: IO = 1 mA DO: IO = 1 mA DO: IO = 5 mA BO2 to BO5, BOF, IO1, IO2: IO = 1 mA VOL4 VOL5 IIH1 IIH2 Input high-level voltage IIH3 IIH4 IIH5 IIH6 IIL1 IIL2 Input low-level current IIL3 IIL4 IIL5 IIL6 Output off leakage current High-level tree-state off leakage current Low-level tree-state off leakage current Input capacitance IOFF1 IOFF2 IOFFH IOFFL CIN IDD1 Current drain IDD2 IDD3 BO2 to BO5, BOF, IO1, IO2: IO = 5 mA BO2 to BO5, BOF, IO1, IO2: IO = 8 mA AOUT: IO = 1 mA, AIN = 1.3 V CE, CL, DI: VI = 6.5 V IO1, IO2: VI = 13 V XIN: VI = VDD FMIN, AMIN: VI = VDD IFIN: VI = VDD AIN: VI = 6.5 V CE, CL, DI: VI = 0 V IO1, IO2: VI = 0 V XIN: VI = 0 V FMIN, AMIN: VI = 0 V IFIN: VI = 0 V AIN: VI = 0 V BO1 to BO5, BOF, AOUT, IO1, IO2: VO = 13 V DO: VO = 6.5 V PD: VO = VDD PD: VO = 0 V FMIN VDD: Xtal = 75 kHz, fIN2 = 130 MHz, VIN2 = 40 mVrms VDD: PLL block stopped (PLL inhibit), Xtal oscillator operating (Xtal = 75 kHz) VDD: PLL block stopped, Xtal oscillator stopped 0.01 0.01 6 5 0.1 10 10 0.3 4.0 8.0 0.6 0.3 4.0 8.0 0.6 VDD - 1.0 1.0 0.5 1.0 0.2 1.0 0.2 1.0 1.6 0.5 5.0 5.0 1.4 22 44 200 5.0 5.0 1.4 22 44 200 5.0 5.0 200 200 Conditions min typ 8.0 500 500 250 200 200 250 0.1 VDD max Unit M k k k k k k V V V V V V V V V V V A A A A A nA A A A A A nA A A nA nA pF mA mA A
Output low-level voltage
No. 5038-5/23
LC72136, 72136M Pin Functions
Symbol Pin No. (MFP pin numbers are in parentheses.) Type Functions Circuit configuration
XIN XOUT
1 (1) 22 (24)
Xtal
* Crystal oscillator connections (75 kHz) * The extremely high input impedance of the XIN pins means that applications must take the possibility of leakage into account.
FMIN
16 (17)
Local oscillator signal input
* FMIN is selected when the serial data input DVS bit is set to 1. * The input frequency range is from 10 to 160 MHz. * The input signal passes through the internal divide-bytwo prescaler and is input to the swallow counter. * The divisor can be in the range 272 to 65535. However, since the signal has passed through the divide-by-two prescaler, the actual divisor is twice the set value.
AMIN
15 (16)
Local oscillator signal input
* AMIN is selected when the serial data input DVS bit is set to 0. * When the serial data input SNS bit is set to 1: -- The input frequency range is 2 to 40 MHz. -- The signal is directly input to the swallow counter. -- The divisor can be in the range 272 to 65535, and the divisor used will be the value set. * When the serial data input SNS bit is set to 0: -- The input frequency range is 0.5 to 10 MHz. -- The signal is directly input to a 12-bit programmable divider. -- The divisor can be in the range 4 to 4095, and the divisor used will be the value set.
CE
3 (4)
Chip enable
* Set this pin high when inputting (DI) or outputting (DO) serial data.
CL
5 (6)
Clock
* Used as the synchronization clock when inputting (DI) or outputting (DO) serial data.
DI
4 (5)
Input data
* Inputs serial data transferred from the controller to the LC72136.
DO
6 (7)
Output data
* Outputs serial data transferred from the LC72136 to the controller. The data output is determined by the DOC0 to DOC2 bits in the serial data.
VDD
17 (18)
Power supply
* The LC72136 power supply pin. (VDD = 4.5 to 5.5 V) * The power on reset circuit operates when power is first applied. * The LC72136 ground
VSS
21 (22)
Ground
Continued on next page. No. 5038-6/23
LC72136, 72136M
Continued from preceding page.
Pin No. (MFP pin numbers are in parentheses.)
Symbol
Type
Functions
Circuit configuration
BO1 BO2 BO3 BO4 BO5
7 (8) 8 (9) 9 (10) 10 (11) 14 (15) Output ports
BOF
2 (3)
* Dedicated outputs * The output states are determined by the BO1 to BO5 bits in the serial data. Data: 0 = open, 1= low * A time base signal (8 Hz) can be output from the BO1 pin. (When the serial data TBC bit is set to 1.) * Care is required when using the BO1 pin, since it has a higher on impedance that the other output ports (pins BO2 to BO5). * The output state of the BOF pin is determined by the serial data DVS bit. Thus this pin can be used as an FM band selection switch. (Note that it should not be used as an AM band selection switch since it is susceptible to noise from the crystal oscillator.) DVS data: 0 = open, 1 = low * All output ports are set to the open state following a power on reset.
IO1 IO2
11 (12) 13 (14)
Input or output ports
* I/O dual-use pins * The direction (input or output) is determined by bits IOC1 and IOC2 in the serial data. Data: 0 = input port, 1 = output port * When specified for use as input ports: The state of the input pin is transmitted to the controller over the DO pin. Input state: low = 0 data value high = 1 data value * When specified for use as output ports: The output states are determined by the IO1 and IO2 bits in the serial data. Data: 0 = open, 1 = low * These pins function as input pins following a power on reset.
PD
18 (19)
Charge pump output
* PLL charge pump output When the frequency generated by dividing the local oscillator signal frequency by N is higher than the reference frequency, a high level is output from the PD pin. Similarly, when that frequency is lower, a low level is output. The PD pin goes to the high-impedance state when the frequencies match.
AIN AOUT
19 (20) 20 (21)
LPF amplifier transistor connections
* The n-channel MOS transistor used for the PLL active low-pass filter.
IFIN
12 (13)
IF counter
* Accepts an input in the frequency range 0.4 to 12 MHz. * The input signal is directly transmitted to the IF counter. * The result is output starting the MSB of the IF counter using the DO pin. * Four measurement periods are supported: 4, 8, 32, and 64 ms.
No. 5038-7/23
LC72136, 72136M Serial Data I/O Procedures The LC72136 inputs and outputs data using the Sanyo CCB (computer control bus) audio LSI serial bus format. This LSI adopts an 8-bit address format CCB.
I/O mode Address B0 B1 B2 B3 A0 A1 A2 A3 Function
1
IN1 (82)
0
0
0
1
0
1
0
0
* Control data input mode (serial data input) * 24 data bits are input. * See the "DI Control Data (serial data input) Structure" item for details on the meaning of the input data.
2
IN2 (92)
1
0
0
1
0
1
0
0
* Control data input mode (serial data input) * 24 data bits are input. * See the "DI Control Data (serial data input) Structure" item for details on the meaning of the input data.
3
OUT (A2)
0
1
0
1
0
1
0
0
* Data output mode (serial data output) * The number of bits output is equal to the number of clock cycles. * See the "DO Output Data (Serial Data Output) Structure" item for details on the meaning of the output data.
No. 5038-8/23
LC72136, 72136M DI Control Data (serial data input) Structure 1. IN1 Mode
2. IN2 Mode
No. 5038-9/23
LC72136, 72136M DI Control Data Functions
No. Control block/data Description Related data
Programmable divider data * Data that sets the programmable divider P0 to P15 A binary value in which P15 is the MSB. The LSB changes depending on DVS and SNS. DVS 1 0 0 (1) DVS, SNS SNS * 1 0 LSB P0 P0 P4 Divisor setting (N) 272 to 65535 272 to 65535 4 to 4095 Actual divisor Twice the value of the setting The value of the setting The value of the setting
Note: P0 to P3 are ignored when P4 is the LSB. * Selects the signal input pin (AMIN or FMIN) for the programmable divider, switches the frequency range, and determines the BOF pin output state. (*: Don't care.) DVS 1 0 SNS * 1 Input pin FMIN AMIN Input frequency range 10 to 160 MHz 2 to 40 MHz BOF pin Low Open Open
0 0 AMIN 0.5 to 10 MHz Note: See the "Programmable Divider" item for details. Reference divider data R0 to R3 * Reference frequency (fref) selection data R3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 R2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 R1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 R0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
Reference frequency (kHz) 25 25 25 25 12.5 6.25 3.125 3.125 5 5 5 1 3 15 PLL INHIBIT + Xtal OSC STOP
(2)
1 1 1 1 PLL INHIBIT Note: PLL INHIBIT The programmable divider and IF counter blocks are stopped, the FMIN, AMIN, and IFIN pins go to the pulled-down state, and the charge pump output pin goes to the high-impedance state. XS * Oscillator margin selection data XS = 0: "Reduction mode" The oscillator margin is reduced and the crystal radiation is reduced. XS = 1: Normal mode. Normal mode is selected following a power-on reset. * IF counter measurement start specification CTE = 1: Counter start CTE = 0: Counter reset * IF counter measurement time determination GT1 0 0 1 1 I/O port specification data IOC1, IOC2 Output port data BO1 to BO5, IO1, IO2 GT0 0 1 0 1 Measurement time (ms) 4 8 32 64 Wait time (ms) 3 to 4 3 to 4 7 to 8 7 to 8 IFS
IF counter control data CTE GT0, GT1 (3)
Note: See the "IF Counter Structure" item for details. (4) * Data that specifies input or output for the I/O dual-use pins Data: 0 = input mode, 1 = output mode * BO1 to BO5, IO1, and IO2 output state data Data: 0 = open, 1 = low * "Data = 0: Open" is selected following a power-on reset. IOC1 IOC2
(5)
Continued on next page. No. 5038-10/23
LC72136, 72136M
Continued from preceding page.
No. Control block/data DO pin control data DOC0, DOC1, DOC2 * Data that determines DO pin output DOC2 0 0 0 0 1 1 1 1 DOC1 0 0 1 1 0 0 1 1 DOC0 0 1 0 1 0 1 0 1 DO pin state Open Low when the unlock state is detected end-UC*1 Open Open The IO1 pin state*2 The IO2 pin state*2 Open Description Related data
The open state is selected following a power-on reset. Note: 1. end-UC: IF counter measurement completion check (6) UL0, UL1, CTE, IOC1, IOC2
When end-UC is set and an IF count is started (CTE = 0 1), the DO pin automatically goes to the open state. When the IF count measurement completes, the DO pin goes low and the count completion check operation is enabled. The DO pin goes to the open state due to serial data I/O (CE: high). 2. Goes to the open state if the IO pin itself is set to be an output port. Caution: The DO pin always goes to the open state during the data input period (during the period when CE is high in mode IN1 or IN2), regardless of the values of the DO pin control data (DOC0 to DOC2). Also, the DO pin outputs the content of the internal DO serial data in synchronization with the CL pin signal during the data output period (during the period when CE is high in the OUT mode) regardless of the values of the DO pin control data (DOC0 to DOC2). Unlock detection data UL0, UL1 * Selects the phase error (oE) detection range for PLL lock discrimination. When a phase error greater than the specified range occurs, the LC72136 determines that the PLL is unlocked. (*: Don't care.) UL1 0 0 1 Phase comparator control data DZ0, DZ1 UL0 0 1 * oE detection width Stopped 0 6.67 s Open oE is output directly oE is extended by 1 to 2 ms Detector output DOC0, DOC1, DOC2
(7)
Note: When unlocked, the DO pin goes low and the serial data output UL bit is 0. * Phase comparator dead zone control data DZ1 0 (8) 0 1 1 DZ0 0 1 0 1 DZA DZB DZC DZD Dead zone mode
Dead zone width: DZA < DZB < DZC < DZD (9) Clock time base TBC Charge pump control data DLC * An 8 Hz 40% duty clock time base signal can be output from BO1 by setting TBC to 1. (The BO1 data will be ignored.) * Data that forcibly controls the charge pump output DLC 0 (10) Normal operation Charge pump output BO1
1 Forced low Note: The LC72136 provides a technique for escaping from deadlock by setting Vtune to VCC (deadlock clearing circuit). This is used when the circuit is deadlocked due to the VCO oscillator being stopped by the VCO control voltage (Vtune) being 0 V. This function goes to the forced low state (DLC = 1) following a power on reset. The crystal oscillator circuit must be operating normally before this data is changed to return to the normal operating (DLC = 0) state.
Continued on next page. No. 5038-11/23
LC72136, 72136M
Continued from preceding page.
No. (11) Control block/data IF counter control data IFS Description * This data should be set to 1 in normal operation. Setting this data to 0 switches the LC72136 to a reduced input sensitivity mode in which the sensitivity is reduced by 10 to 30 mVrms. * See the "IF Counter Operation" item for details. * LSI test data TEST0 TEST1 All three bits must be set to 0. TEST2 All the test data is set to 0 following a power-on reset. Related data
LSI test data TEST 0 to 3 (12)
DO Output Data (Serial Data Output) Structure 3. OUT mode
DO Output Data
No. Control block/data I/O port data I2, I1 Description * Data latched from the states of the I/O ports, pins IO1 and IO2. (This data reflects the pin states, regardless of whether they are in input or output mode.) I1 IO1 pin state High: 1 I2 IO2 pin state Low: 0 * Data latched from the state of the unlock detection circuit UL 0: Unlocked UL 1: Locked or in detection stopped mode * Data latched from the state of the IF counter, which is a 20-bit binary counter. C19 Binary counter MSB C0 Binary counter LSB Related data IOC1, IOC2
(1)
(2)
PLL unlock data UL IF counter binary data C19 to C0
UL0, UL1 CTE, GT0, GT1
(3)
No. 5038-12/23
LC72136, 72136M Serial Data Input (IN1/IN2) tSU, tHD, tEL, tES, tEH, 0.75 s tLC < 0.75 s 1. CL: Normal high
2. CL: Normal low
Serial Data Output (OUT) tSU, tHD, tEL, tES, tEH, 0.75 s tDC, tDH < 0.35 s 1. CL: Normal high
2. CL: Normal low
Note: Since the DO pin is an n-channel open drain circuit, the times for the data to change (tDC and tDH) will differ depending on the value of the pull-up resistor, printed circuit board capacitance.
No. 5038-13/23
LC72136, 72136M Serial Data Timing
CL Stopped at the Low Level
CL Stopped at the High Level
Parameter Data setup time Data hold time Clock low-level time Clock high-level time CE wait time CE setup time CE hold time Data latch change time Data output time Symbol tSU tHD tCL tCH tEL tES tEH tLC tDC tDH DO, CL These times depend on the pull-up resistance DO, CE and the printed circuit board capacitances. Pins DI, CL DI, CL CL CL CE, CL CE, CL CE, CL Conditions min 0.75 0.75 0.75 0.75 0.75 0.75 0.75 0.75 0.35 0.35 typ max Unit s s s s s s s s s s
No. 5038-14/23
LC72136, 72136M Programmable Divider Structure
DVS A B C 1 0 0
SNS * 1 0
Input pin FMIN AMIN AMIN
Set divisor 272 to 65535 272 to 65535 4 to 4095
Actual divisor: N Twice the set value The set value The set value
Input frequency range (MHz) 10 to 160 2 to 40 0.5 to 10
Note: * Don't care.
Sample Programmable Divider Divisor Calculations 1. For a 50 kHz FM step size (DVS = 1, SNS = *: FMIN selected) * FM RF = 90.0 MHz (IF = +10.7 MHz) FM VCO = 100.7 MHz PLL fref = 25 kHz (R0 to R1 = 1, R2 to R3 = 0) 100.7 MHz (FM VCO) / 25 kHz (fref) / 2 (FMIN: divide-by-two prescaler) = 2014 07DE (HEX)
2. For a 5 kHz SW step size (DVS = 0, SNS = 1: AMIN high-speed side selected) * SW RF = 21.75 MHz (IF = +450 kHz) SW VCO = 22.20 MHz PLL fref = 5 kHz (R0 = R2 = 0, R1 = R3 = 1) 22.2 MHz (SW VCO) / 5 kHz (fref) = 4440 1158 (HEX)
3. For a 9 kHz MW step size (DVS = 0, SNS = 0: AMIN low-speed side selected) * MW RF = 1008 kHz (IF = +450 kHz) MW VCO = 1458 kHz PLL fref = 3 kHz (R0 to R1 = 0, R2 to R3 = 1): using a 3 kHz reference frequency 1458 kHz (MW VCO) / 3 kHz (fref) = 486 1E6 (HEX)
No. 5038-15/23
LC72136, 72136M IF Counter Structure The LC72136 IF counter is a 20-bit binary counter. The result of the count can be read out serially, MSB first, from the DO pin.
GT1 0 0 1 1
GT0 0 1 0 1
Measurement time Measurement period (GT) (ms) 4 8 32 64 Wait time (tWU) (ms) 3 to 4 3 to 4 7 to 8 7 to 8
IF frequency (Fc) measurement consists of determining how many pulses enter the IF counter in a specified measurement time (GT). Fc = C GT (C = Fc x GT) C: count value (number of pulses)
Sample IF Counter Frequency Calculations 1. For a measurement time (GT) of 32 ms and a count value (C) of 53980 (hexadecimal), which is 342,400 (decimal) IF frequency (Fc) = 342,400 / 32 ms = 10.7 MHz
2. For a measurement time (GT) of 8 ms and a count value (C) of E10 (hexadecimal), which is 3600 (decimal) IF frequency (Fc) = 3600 / 8 ms = 450 kHz
No. 5038-16/23
LC72136, 72136M IF Counter Operation
Before starting the IF count, the IF counter must be reset in advance by setting CTE in the serial data to 0. The IF count is started by changing the CTE bit in the serial data from 0 to 1. The serial data is latched by the LC72136 when the CE pin is dropped from high to low. The IF signal must be supplied to the IFIN pin in the period between the point the CE pin goes low and the end of the wait time at the latest. Next, the value of the IF count at the end of the measurement period must be read out during the period CTE is 1. This is because the IF counter is reset when CTE is set to 0. Note: When operating the IF counter, the control microprocessor must first check the state of the IF-IC SD (station detect) signal and only after determining that the SD signal is present turn on IF buffer output and execute an IF count operation. Auto-search techniques that use only the IF counter are not recommended, since it is possible for IF buffer leakage output to cause incorrect stops at points where there is no station. IFIN Minimum Sensitivity Ratings
f (MHz) IFS 1: Normal mode 0: Degradation mode 0.4 f < 0.5 40 mVrms (0.1 to 3 mVrms) 70 mVrms (10 to 15 mVrms) 0.5 f < 8 40 mVrms 70 mVrms 8 f 12 40 mVrms (1 to 10 mVrms) 70 mVrms (30 to 40 mVrms)
Note: Values in parentheses are actual performance values presented as reference data.
Unlock Detection Timing 1. Unlock Detection Determination Timing Unlock detection is performed in the reference frequency (fref) period (interval). Therefore, in principle, unlock determination requires a time longer than the period of the reference frequency. However, immediately after changing the divisor N (frequency) unlock detection must be performed after waiting at least two periods of the reference frequency.
No. 5038-17/23
LC72136, 72136M
Figure 1 Unlock Detection Timing For example, if fref is 1 kHz (and thus the period is 1 ms), after changing the divisor N, the system must wait at least 2 ms before checking for the unlocked state.
Figure 2 Circuit Structure
No. 5038-18/23
LC72136, 72136M 2. Unlock Detection Software
Figure 3 3. When Outputting Unlock Data Using Serial Data Output: Once the LC72136 detects an unlocked state, it does not reset the unlock data (UL) until the next data output (or data input) operation is performed. At the data output point in Figure 3, although the VCO frequency is stable (locked), the unlock data remains set to the unlocked state since no data output has been performed since the value of N was changed. Thus, even though the frequency became stable (locked), from the point of view of the data, the circuit is in the unlocked state. Therefore, the data output immediately following a change to the value of N should be seen as a dummy data, and the data from the second data output (data output ) and later outputs should be seen as valid data.
Lock Determination Flowchart
No. 5038-19/23
LC72136, 72136M When directly outputting data from the DO pin (set up by the DO pin control data) Since the DO pin outputs the unlocked state (locked: high, unlocked: low) the timing considerations in the technique described in the previous section are not necessary. After changing the value of N, the locked state can be determined after waiting at least two periods of the reference frequency. Notes on Clock Time Base Usage When the clock time base output is used, the value of the pull-up resistor for the output pin (BO1) must be at least 100 k. This is to avoid degradation of the VCO C/N characteristics when using the built-in low-pass filter transistor to form the loop filter. Since the clock time base output pin and the low-pass filter transistor ground are the same node in the IC, the time base output pin current fluctuations must be suppressed to limit the influence on the low-pass filter. We recommend the use of a Schmitt input on the receiving controller (microprocessor) to prevent chattering.
Other Items 1. Notes on the Phase Comparator Dead Zone
DZ1 0 0 1 1 DZ0 0 1 0 1 Dead-zone mode DZA DZB DZC DZD Charge pump ON/ON ON/ON OFF/OFF OFF/OFF Dead zone - -0 sec -0 sec +0 sec + +0 sec
Since correction pulses are output from the charge pump even if the PLL is locked when the charge pump is in the ON/ON state, the loop can easily become unstable. This point requires special care when designing application circuits. The following problems may occur in the ON/ON state. * Side band generation due to reference frequency leakage * Side band generation due to both the correction pulse envelope and low frequency leakage
No. 5038-20/23
LC72136, 72136M Schemes in which a dead zone is present (OFF/OFF) have good loop stability, but have the problem that acquiring a high C/N ratio can be difficult. On the other hand, although it is easy to acquire a high C/N ratio with schemes in which there is no dead zone, it is difficult to achieve high loop stability. Therefore, it can be effective to select DZA or DZB, which have no dead zone, in applications which require an FM S/R ratio in excess of 90 to 100 dB, or in which an increased AM stereo pilot margin is desired. On the other hand, we recommend selecting DZC or DZD, which provide a dead zone, for applications which do not require such a high FM signal-to-noise ratio and in which either AM stereo is not used or an adequate AM stereo pilot margin can be achieved. Dead Zone The phase comparator compares fp to a reference frequency (fr) as shown in Figure 4. Although the characteristics of this circuit (see Figure 5) are such that the output voltage is proportional to the phase difference o (line A), a region (the dead zone) in which it is not possible to compare small phase differences occurs in actual ICs due to internal circuit delays and other factors (line B). A dead zone as small as possible is desirable for products that must provide a high S/N ratio. However, since a larger dead zone makes this circuit easier to use, a larger dead zone is appropriate for popularlypriced products. This is because it is possible for RF signals to leak from the mixer to the VCO and modulate the VCO in popularly-priced products in the presence of strong RF inputs. When the dead zone is narrow, the circuit outputs correction pulses and this output can further modulate the VCO and generate beat frequencies with the RF signal.
Figure 4
Figure 5 2. Notes on the FMIN, AMIN, and IFIN Pins Coupling capacitors must be placed as close as possible to their respective pin. A capacitance of about 100 pF is desirable. In particular, if a capacitance of 1000 pF or over is used for the IF pin, the time to reach the bias level will increase and incorrect counting may occur due to the relationship with the wait time. 3. Notes on IF Counting SD must be used in conjunction with the IF counting time When using IF counting, always implement IF counting by having the microprocessor determine the presence of the IF-IC SD (station detect) signal and turn on the IF counter buffer only if the SD signal is present. Schemes in which auto-searches are performed with only IF counting are not recommended, since they can stop at points where there is no signal due to leakage output from the IF counter buffer.
No. 5038-21/23
LC72136, 72136M 4. DO Pin Usage Techniques In addition to data output mode times, the DO pin can also be used to check for IF counter count completion and for unlock detection output. Also, an input pin state can be output unchanged through the DO pin and input to the controller. 5. Power Supply Pins A capacitor of at least 2000 pF must be inserted between the power supply VDD and VSS pins for noise exclusion. This capacitor must be placed as close as possible to the VDD and VSS pins. Pin States Following a Power-On Reset
No. 5038-22/23
LC72136, 72136M Sample Application System (Using the DIP22S package)
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of October, 1995. Specifications and information herein are subject to change without notice. PS No. 5038-23/23

▲Up To Search▲

Price & Availability of LC72136

	To Download LC72136 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .